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Standard Products
UT69RH051 Radiation-Hardened MicroController
Data Sheet June 2004
FEATURES Three 16-bit timer/counters - High speed output - Compare/capture - Pulse width modulator - Watchdog timer capabilities 256 bytes of on-chip data RAM 32 programmable I/O lines 7 interrupt sources Programmable serial channel with: - Framing error detection - Automatic address recognition TTL and CMOS compatible logic levels 64K external data and program memory space MCS-51 fully compatible instruction set Flexible clock operation - 1Hz to 20MHz with external clock - 2MHz to 20MHz using internal oscillator with external crystal Radiation-hardened process and design; total dose irradiation testing MIL-STD-883 Method 1019 - Total dose: 1.0E6 rads(Si) - Latchup immune Packaging options: - 40-pin 100-mil center DIP (0.600 x 2.00) - 44-lead 25-mil center Flatpack (0.670 x 0.800) Standard Microcircuit Drawing 5962-95638 available - QML Q & V compliant
RAM ADDRESS REGISTER
PORT 0 DRIVERS
PORT 2 DRIVERS
RAM
PORT 0 LATCH
PORT 2 LATCH
PROGRAM ADDRESS REGISTER BUFFER PC INCREMENTER PROGRAM COUNTER DPTR
B REGISTER
ACC TMP2 ALU TMP1
PSEN ALE EA RST
INSTRUCTION REGISTER
MICROSEQUENCER
PSW
TMP3
STACK POINTER SPECIAL FUNCTION REGISTERS, TIMERS, PCA, SERIAL PORT
PORT 1 LATCH PORT 1 DRIVERS
PORT 3 LATCH PORT 3 DRIVERS
OSC.
XTAL1
XTAL2 P1.0 - P1.7 P3.0 - P3.7
Figure 1. UT69RH051 MicroController Block Diagram
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1.0 INTRODUCTION The UT69RH051 is a radiation-tolerant 8-bit microcontroller that is pin equivalent to the MCS-51 industry standard microcontroller when in a 40-pin DIP. The UT69RH051's static design allows operation from 1Hz to 20MHz. This data sheet describes hardware and software interfaces to the UT69RH051. 2.0 SIGNAL DESCRIPTION VDD: +5V Supply voltage VSS: Circuit Ground Port 0 (P0.0 - P0.7): Port 0 is an 8-bit port. Port 0 pins are used as the low-order multiplexed address and data bus during accesses to external program and data memory. Port 0 pins use internal pullups when emitting 1's and are TTL compatible. Port 1 (P1.0 - P1.7): Port 1 is an 8-bit bidirectional I/O port with internal pullups. The output buffers can drive TTL loads. When the Port 1 pins have 1's written to them, they are pulled high by the internal pullups and can be used as inputs in this state. As inputs, any pins that are externally pulled low sources current because of the pullups. In addition, Port 1 pins have the alternate uses shown in table 1. Port 2 (P2.0 - P2.7): Port 2 is an 8-bit port. Port 2 pins are used as the high-order address bus during accesses to external Program Memory and during accesses to external Data Memory that uses 16-bit addresses (i.e., MOVX@DPTR). Port 2 uses internal pullups when emitting 1's in this mode. During operations that do not require a 16-bit address, Port 2 emits the contents of the P2 Special Function Registers (SFR). The pins have internal pullups and drives TTL loads. Port 3 (P3.0 - P3.7): Port 3 is an 8-bit bidirectional I/O port with internal pullups. The output buffers can drive TTL loads. When the Port 3 pins have 1's written to them, they are pulled high by the internal pullups and can be used as inputs in this state. As inputs, any pins that are externally pulled low sources current because of the pullups. In addition, Port 3 pins have the alternate uses shown in table 2. P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 Port Pin P1.0 P1.1
Table 1. Port 1 Alternate Functions Alternate Name T2 T2EX ECI CEX0 CEX1 CEX2 CEX3 CEX4 Alternate Function External clock input to Timer/ Counter 2 Timer/Counter 2 Capture/Reload trigger and direction control External count input to PCA External I/O for PCA capture/ compare Module 0 External I/O for PCA capture/ compare Module 1 External I/O for PCA capture/ compare Module 2 External I/O for PCA capture/ compare Module 3 External I/O for PCA capture/ compare Module 4
Table 2. Port 3 Alternate Functions Port Pin P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Alternate Name RXD TXD INT0 INT1 T0 T1 WR RD Alternate Function Serial port input Serial port output External interrupt 0 External interrupt 1 External clock input for Timer 0 External clock input for Timer 1 External Data Memory write strobe External Data Memory read strobe
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RST: Reset Input. A high on this input for 24 oscillator periods while the oscillator is running resets the device. All ports and SFRs reset to their default conditions. Internal data memory is undefined after reset. Program execution begins within 12 oscillator periods (one machine cycle) after the RST signal is brought low. RST contains an internal pulldown resistor to allow implementing power-up reset with only an external capacitor. ALE: Address Latch Enable. The ALE output is a pulse for latching the low byte of the address during accesses to external memory. In normal operation, the ALE pulse is output every sixth oscillator cycle and may be used for external timing or clocking. However, during each access to external Data Memory (MOVX instruction), one ALE pulse is skipped. PSEN: Program Store Enable. This active low signal is the read strobe to the external program memory. PSEN activates every sixth oscillator cycle except that two PSEN activations are skipped during external data memory accesses. EA: External Access Enable. This pin should be strapped to V SS (Ground) for the UT69RH051. XTAL1: Input to the inverting oscillator amplifier. XTAL2: Output from the inverting oscillator amplifier.
2.1 Hardware/Software Interface 2.1.1 Memory The UT69RH051 has a separate address space for Program and Data Memory. Internally, the UT69RH051 contains 256 bytes of Data Memory. It addresses up to 64Kbytes of external Data Memory and 64Kbytes of external Program Memory. 2.1.1.1 Program Memory There is no internal program memory in the UT69RH051. All program memory is accessed as external through ports P0 and P2. The EA pin must be tied to VSS (ground) to enable access to external locations 0000H through 7FFFH. Following reset, the UT69RH051 fetches the first instruction at address 0000h. 2.1.1.2 Data Memory The UT69RH051 implements 256 bytes of internal data RAM. The upper 128 bytes of this RAM occupy a parallel address space to the SFRs. The CPU determines if the internal access to an address above 7F H is to the upper 128 bytes of RAM or to the SFR space by the addressing mode of the instruction. If direct addressing is used, the access is to the SFR space. If indirect addressing is used, the access is to the internal RAM. Stack operations are indirectly addressed so the upper portion of RAM can be used as stack space. Figure 3 shows the organization of the internal Data Memory. The first 32 bytes are reserved for four register banks of eight bytes each. The processor uses one of the four banks as its working registers depending on the RS1 and RS0 bits in the PSW SFR. At reset, bank 0 is selected. If four register banks are not required, use the unused banks as general purpose scratch pad memory. The next 16 bytes (128 bits) are individually bit addressable. The remaining bytes are byte addressable and can be used as general purpose scratch pad memory. For addresses 0 - 7FH, use either direct or indirect addressing. For addresses larger than 7FH, use only indirect addressing. In addition to the internal Data Memory, the processor can access 64Kbytes of external Data Memory. The MOVX instruction accesses external Data Memory. 2.1.2 Special Function Registers Table 3 contains the SFR memory map. Unoccupied addresses are not implemented on the device. Read accesses to these addresses will return unknown values and write accesses will have no effect.
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(T2) (T2EX) (ECI) (CEX0) (CEX1) (CEX2) (CEX3) (CEX4) (RXD) (TXD) (INT0) (INT1) (T0) (T1) (WR) (RD)
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 XTAL2 XTAL1 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VDD P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 EA ALE PSEN P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0
(AD0) (AD1) (AD2) (AD3) (AD4) (AD5) (AD6) (AD7)
(A15) (A14) (A13) (A12) (A11) (A10) (A9) (A8)
Figure 2a. UT69RH051 40-Pin DIP Connections
(T2) (T2EX) (ECI) (CEX0) (CEX1) (CEX2) (CEX3) (CEX4) (RXD) (TXD) (INTO) (INT1) (TO) (T1) (WR) (RD)
VSS P1.0 P1.1 NC P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 XTAL2 XTAL1 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
VDD P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 EA ALE PSEN P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 NC VDD
(AD0) (AD1) (AD2) (AD3) (AD4) (AD5) (AD6) (AD7)
(A15) (A14) (A13) (A12) (A11) (A10) (A9) (A8)
Figure 2b. UT69RH051 44-Pin Flatpack Connections
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8 BYTES F8 F0 INDIRECT ACCESS ONLY FF F7
* * *
88 80 78 70
* * *
8F 87 7F 77 SCRATCH PAD AREA
* * *
38 DIRECT OR INDIRECT ACCESS 30 28 20 18 10 08 00
* * *
3F 37 2F 27 1F 17 0F 07 REGISTER BANKS BIT ADDRESSABLE SEGMENT
Figure 3. Internal Data Memory Organization
2.1.3 Reset The reset input is the RST pin. To reset, hold the RST pin high for a minimum of 24 oscillator periods while the oscillator is running. The CPU generates an internal reset from the external signal. The port pins are driven to the reset state as soon as a valid high is detected on the RST pin.
While RST is high, PSEN and the port pins are pulled high; ALE is pulled low. All SFRs are reset to their reset values as shown in table 3. The internal Data Memory content is indeterminate. The processor will begin operation one machine cycle after the RST line is brought low. A memory access occurs immediately after the RST line is brought low, but the data is not brought into the processor. The memory access repeats on the next machine cycle and actual processing begins at that time.
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Table 3. SFR Memory Registers
F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 IP X0000000 P3 11111111 IE 00000000 P2 11111111 SCON 00000000 P1 11111111 TCON 00000000 P0 11111111 TMOD 00000000 SP 00000111 TL0 00000000 DPL 00000000 TL1 00000000 DPH 00000000 TH0 00000000 TH1 00000000 PCON 00XX00XX SBUF XXXXXXXX SADDR 00000000 SADEN 00000000 IPH X00000000 ACC 00000000 CCON 00X00000 PSW 00000000 T2CON 00000000 T2MOD XXXXXX00 RCAP2L 00000000 RCAP2H 00000000 TL2 00000000 TH2 00000000 CMOD OOXXX000 CCAPM0 X00000000 CCAPM1 X00000000 CCAPM2 X00000000 CCAPM3 X00000000 CCAPM4 X00000000 B 00000000 CL 00000000 CCAP0L CCAP1L CCAP2L CCAP3L CCAP4L XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX CH 00000000 CCAP0H CCAP1H CCAP2H CCAP3H CCAP4H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX FF F7 EF E7 DF D7 CF C7 BF B7 AF A7 9F 97 8F 87
Notes: 1. Values shown are the reset values of the registers. 2. X = undefined.
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3.0 RADIATION HARDNESS The UT69RH051 incorporates special design and layout features which allow operation in high-level radiation environments. UTMC has developed special low-temperature processing techniques designed to enhance the total-dose radiation hardness of both the gate oxide and the field oxide while maintaining the RADIATION HARDNESS DESIGN SPECIFICATIONS 1 Total Dose LET Threshold Neutron Fluence Saturated Cross-Section (1Kx8) Single Event Upset Single Event Latchup1
Note: 1. Worst case temperature TA = +125C. 2. Adams 90% worst case environment (geosynchronous).
circuit density and reliability. For transient radiation hardness and latchup immunity, UTMC builds all radiation-hardened products on epitaxial wafers using an advanced twin-tub CMOS process. In addition, UTMC pays special attention to power and ground distribution during the design phase, minimizing doserate upset caused by rail collapse.
1.0E6 20 1.0E14 1E-4 1.3E-7 LET>126
rad(Si) MeV-cm2/mg n/cm2 cm2/device errors/device-day2 MeV-cm2/mg
4.0 ABSOLUTE MAXIMUM RATINGS 1 (Referenced to V SS) SYMBOL VDD VI/O TSTG PD TJ JC II PARAMETER DC Supply Voltage Voltage on Any Pin Storage Temperature Maximum Power Dissipation Maximum Junction Temperature Thermal Resistance, Junction-to-Case 2 DC Input Current LIMITS -0.5 to 7.0 -0.5 to VDD+0.3V -65 to +150 750 175 10 UNITS V V C mW C C/W mA
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Notes: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Test per MIL-STD-883, Method 1012.
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5.0 DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)* VDD = 5.0V 10%; TA = -55C < TC < +125C) SYMBOL VIL VIH VIH1 VOL PARAMETER Low-level Input Voltage High-level Input Voltage (except XTAL, RST) High-level Input Voltage (XTAL) Low-level Output Voltage1 (Ports 1, 2 and 3) IOL = 100A IOL = 1.6mA IOL = 3.5mA VOL1 Low-level Output Voltage1,2 (Port 0, ALE, PSEN, PROG) IOL = 200A IOL = 3.2mA IOL = 7.0mA VOH High-level Output Voltage (Ports 1, 2, and 3 ALE and PSEN)
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CONDITION
MINIMUM 2.0 3.85
MAXIMUM 0.8
UNIT V V V
0.3 0.45 1.0 0.3 0.45 1.0 4.2
V V V V V V V
IOH = -10A
IOH = -30A IOH = -60A VOH1 High-level Output Voltage (Port 0 in External Bus Mode) IOH = -200A IOH = -3.2mA IOH = -7.0mA IIL IIL ILI ILI CIO
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3.8 3.0 4.2 3.8 3.0 -50 -65 -65 25 65 65 15 95 120
V V V V V A A A A pF mA
Logical 0 Input Current (Ports 1, 2, and 3) Logical 0 Input Current (XTAL 1) Input Leakage Current (Port 0) Input Leakage Current (XTAL1) Pin Capacitance Power Supply Current:
VIN = 0.0V VCC = 5.5V VIN = 0.0V VCC = 5.5V VIN = 0.0V or VCC VCC = 5.5V VIN = 0.0V or VCC VCC = 5.5V @ 1MHZ, 25C @16MHz @20 MHz
IDD
Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883. 1. Under steady state (non-transient) conditions, I OL must be limited externally as follows: Maximum IOL per port pin: 10mA Maximum IOL per 8-bit portPort 0: 26mA Ports 1, 2, & 3: 15mA Maximum total I OL for all output pins: 71mA If IOL exceeds the test condition, V OL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1 to 0 transitions during bus operations. In applications where capacitance loading exceeds 100 pF, the noise pulse on the ALE may exceed 0.8V. In these cases, it may be desirable to qualify ALE with a schmitt trigger or use an address latch with a schmitt trigger strobe input. 3. Capacitive loading ports 0 and 2 cause the VOH on ALE and PSEN to drop below the VDD-0.3 specification when the address lines are stabilizing. 4. Capacitance measured for initial qualification or design changes which may affect the value.
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VDD IDD VDD VDD RST P0 EA (NC) CLOCK SIGNAL GND tCLCH = tCHCL = 5ns XTAL2 XTAL1 VSS VDD
Figure 4. IDD Test Condition, Active Mode All other pins disconnected
VDD -0.5 0.45V
0.7 VDD 0.2 V DD -0.1 t CHCL tCHCX tCLCL
tCHCX tCLCH
Figure 5. Clock Signal Waveform for IDD Tests in Active and Idle Modes tCLCH = tCHCL = 5ns
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6.0 AC CHARACTERISTICS READ CYCLE (Post-Radiation)* (VDD = 5.0V 10%; -55C < TC < +125C) SYMBOL tCLCL 1/tCLCL tLHLL tAVLL tLLAX1 tLLIV tLLPL tPLPH tPLIV tPXIX1 tPXIZ1 tAVIV tPLAZ1 tRLRH tWLWH tRLDV tRHDX1 tRHDZ1 tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tQVWH tRLAZ1 tWHLH Clock Period Oscillator Frequency ALE Pulse Width Address Valid to ALE Low Address Hold after ALE Low ALE Low to Valid Instruction ALE Low to PSEN Low PSEN Pulse Width PSEN Low to Valid Instruction In Input Instruction Hold after PSEN Input Instruction Float after PSEN Address to Valid Instruction In PSEN Low to Address Float RD Pulse Width WR Pulse Width RD Low to Valid Data In Data Hold After RD High Data Float After RD High ALE Low Valid Data In Address to Valid Data In ALE Low to RD or WR Low Address Valid to WR Low Data Valid Before WR High Data Hold After WR High Data Valid to WR High RD Low to Address Float RD or WR High to ALE High tCLCL-40 3 tCLCL-50 4 tCLCL-130 tCLCL-33 tCLCL-33 7 tCLCL-150 0 tCLCL+40 0 2 tCLCL-60 8 tCLCL-150 9 tCLCL-165 3 tCLCL+50 6 tCLCL-100 6 tCLCL-100 5 tCLCL-165 0 tCLCL-25 5 tCLCL-105 10 tCLCL-30 3 tCLCL-45 3 tCLCL-105 2 tCLCL-40 tCLCL-40 tCLCL-30 4 tCLCL-100 PARAMETER MINIMUM 50 20 MAXIMUM UNIT ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019 at 1.0E6 rads(Si). 1. Guaranteed, but not tested.
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tLHLL ALE tLLPL tAVLL PSEN tLLAX PORT 0
A0 - A7
tPLPH tLLIV tPLIV tPLAZ tPXIX
INSTR IN A0 - A7
tPXIZ
tAVIV PORT 2
A8 - A15 A8 - A15
Figure 6. External Program Memory Read Timing Waveforms
ALE
tLHLL tLLDV tLLWL tRLRH
tWHLH
PSEN RD tAVLL tRLDV tLLAX PORT 0
A0 -A7 FROM RI OR DPL
tRHDZ t RLAZ tRHDX
DATA IN A0 - A7 FROM PCL INSTR IN
tAVWL tAVDV PORT 2
P2.0 - P2.7 OR A8 -A15 FROM DPH A8 - A15 FROM PCH
Figure 7. External Data Memory Read Cycle Waveforms
ALE
tLHLL
tWHLH
PSEN tLLWL WR tAVLL tLLAX PORT 0
A0 -A7 FROM RI OR DPL
tWLWH tWHQX tQVWH
DATA OUT A0 - A7 FROM PCL INSTR IN
tQVWX
t AVWL PORT 2
P2.0 - P2.7 OR A8 -A15 FROM DPH A8 - A15 FROM PCH
Figure 8. External Data Memory Write Cycle Waveforms
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7.0 SERIAL PORT TIMING CHARACTERISTICS (VDD = 5.0V 10%; -55C < T C < +125C) SYMBOL tXLXL1 tQVXH tXHQX tXHDX1 tXHDV PARAMETER Serial Port Clock Period Output Data Setup to Clock Rising Edge Output Data Hold after Clock Rising Edge Input Data Hold after Clock Rising Edge Clock Rising Edge to Input Data Valid MINIMUM 12 tCLCL-10 10 tCLCL-133 2 tCLCL-70 0 10 tCLCL-133 MAXIMUM 12 tCLCL+10 UNIT ns ns ns ns ns
Note: 1. Guaranteed, but not tested.
0 ALE
1
2
3
4
5
6
7
8
TXLXL CLOCK TXHQX OUTPUT DATA
(WRITE TO SBUF)
TQVXH 0 TXHDV 1 2 TXHDX
VALID VALID VALID VALID VALID VALID
3
4
5
6
7
SET TI
VALID
INPUT DATA
(CLEAR RI)
VALID
SET RI
Figure 9. Serial Port Timing Waveforms 8.0 EXTERNAL CLOCK DRIVE TIMING CHARACTERISTICS SYMBOL 1/tCLCL tCHCX tCLCX tCLCH tCHCL PARAMETER Oscillator Frequency High Time Low Time Rise Time Fall Time 16 16 20 20 MINIMUM MAXIMUM 20 UNIT MHz ns ns ns ns
Note: 1. Guaranteed, but not tested.
VDD - 0.5 0.7 VDD 0.2 V DD - 0.1 tCHCX tCHCL tCLCL tCLCH
0.45 V
tCHCX
Figure 10. External Clock Drive Timing Waveforms 12
9.0 PACKAGING
E 0.595+0.010 S1 0.005 MIN. TYP. S2 0.005 MIN. typ. e 0.100
D 2.000 +0.025 b 0.018
+0.002
PIN 1 I.D. (Geometry OPTIONAL) TOP VIEW
A 0.185 MAX. SIDE VIEW
L 0.200 0.125
C 0.010
+ 0.002 - 0.001
Notes: 1. All package finishes are per MIL-PRF-38535. 2. Letter designations are for cross-reference MIL-STD-1835.
0.600
END VIEW
Figure 11. 40-pin Side-Brazed DIP
13
C
Notes: 1. All exposed metalized areas to be plated per MIL-PRF-38535. 2. Dimension letters refer to MIL-STD-1835.
Figure 12. 44-Lead Flatpack
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APPENDIX A Difference Between Industry Standard and UT69RH051 The areas in which the UT69RH051 differs from the industry standard will be covered in this section. In this discussion, industry standard will be used generically to refer to all speed grades including the 20MHz. 1.0 RESET The UT69RH051 requires the RST input to be held high for at least 24 oscillator periods to guarantee the reset is completed in the chip. Also, the port pins are reset asynchronously as soon as the RST pin is pulled high. On the UT69RH051 all portions of the chip are reset synchronously when the RST pin is high during a rising edge of the input clock. When coming out of reset, the industry standard takes 1 to 2 machine cycles to begin driving ALE and PSEN immediately after the RST is removed, but the access during the first machine cycle after reset is ignored by the processor. The second cycle will repeat the access and processing will begin. 2.0 POWER SAVING MODES OF OPERATION 2.1 Idle Mode Idle mode and the corresponding control bit in the PCON SFR have not been implemented in the UT69RH051. Setting the idle control bit has no effect. 2.2 Power Down Mode Power down mode and the corresponding control bit in the PCON register have not been implemented in the UT69RH051. Setting the power down control bit has no effect. Also, the Power Off Flag in the PCON has not been implemented. 3.0 ON CIRCUIT EMULATION The On Circuit Emulation mode of operation in the industry standard has not been implemented in the UT69RH051. 4.0 OPERATING CONDITIONS The operating voltage range for the industry standard is 5V+20%. The operating temperature range is 0C to 70C. On the UT69RH051, the operating voltage range is 5V+10%. The operating temperature range is -55C to +125C.
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APPENDIX B Impact of External Program ROM The 8051 family of microcontrollers, including the industry standards, use ports 0 and 2 to access external memory. In implementations with external program memory, these two ports are dedicated to the program ROM interface and can not be used as Input/Output ports. The UT69RH051 uses external program ROM, so ports 0 and 2 will not be available for I/O.
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ORDERING INFORMATION
UT69RH051 Microcontroller: SMD 5962 * 95638 * * * *
Lead Finish: (A) = Solder (C) = Gold (X) = Optional Case Outline: (Q) = 40-pin DIP (Y) = 44-pin Flatpack
Class Designator: (Q) = Class Q (V) = Class V Device Type (01) = 8-bit Microcontroller
Drawing Number: 95638 Total Dose: (H) = 1E6 rads(Si) (G) = 5E5 rads(Si) (F) = 3E5 rads(Si) (R) = 1E5 rads(Si) Federal Stock Class Designator: No options
Notes: 1. Lead finish (A, C, or X) must be specified. 2. If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening.
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UT69RH051 Microcontroller
UT ****
*** - * *
**
Total Dose: ( ) = None Lead Finish: (A) = Solder (C) = Gold (X) = Optional Screening: (C) = Mil Temp (P) = Prototype Package Type: (P) = 40-pin DIP (W) = 44-pin Flatpack
Device Type: (UT69RH051) =
8-bit Microcontroller
Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an "X" is specified when ordering, then the part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3. Radiation characteristics are neither tested nor guaranteed and may not be specified. 4. Devices have prototype assembly and are tested at 25C only. Radiation characteristics are neither tested nor guaranteed and may not be specified.
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Notes
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